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RTL-Design & Verification

  • by Devikarani H S
  • English
  • (8 Rating)
About Nexsemi Academy

Nexsemi Academy offers cutting-edge digital solutions and research-driven
training across industries. Recognized as one of India's top technical training providers,
it specializes in RTL Design & Verification, Physical Design, Analog Layout, and more.
Known for unlimited placements, skill enhancement, and world-class training at affordable fees,
Nexsemi ensures students achieve excellent results and secure their first job from Day 1.
Our mission is simple: Equip every student with the best training and placement
opportunities to help them land their dream job.


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Course Description

RTL Design is a crucial part of digital circuit design and refers to the abstraction level at which hardware components are described in terms of data flow and control operations. At this level, the design process involves defining how data moves between registers and how it is processed by combinational logic.

What You’ll Learn?
  • Digital Design
  • Verilog
  • System Verilog
  • Universal Verification Methodology
  • Protocol - AMBA, PCIE & Ethernet



Course Curriculum

Digital Design

  • Boolean Algebra
  • Logic Gates
  • Combinational Logic Design
  • Sequential Logic Design
  • Registers (SISO, SIPO, PISO, PIPO, USR, LFSR)
  • Counters ( Asynchronous & Synchronous)
  • FSM ( Melay and Moore - overlapping & Non overlapping
  • FIFO ( Asynchronous, Synchronous)
Verilog

  • Verilog Modelling Styles
  • Design Methodologies ( TopDown/ Bottom Approach
  • Adders, Latch, Flipflop, counter, FSM, Shift registers
    2 Question15 Minutes
  • Stratified Event Queue or Timming Regions
  • Comparator, Seven Segment Display, Multipliers
  • Synthesizable vs Non-Synthesizable Cpnstructs
  • Race Conditions in Verilog
  • System Tasks
System Verilog

  • SV Architecture.
  • Data Types
  • Tasks and Functions
    2 Question15 Minutes
  • Classes
  • Randomization
  • Constraints
  • ASIC / SoC Verification
  • Procedural Statements and Flow Control
  • Processes
  • Assertion
  • Coverage
Universal Verification Methodology

  • Introduction
  • UVM Testbench Architecture UVM Phases, UVM TLM
  • UVM Reporting, UVM Configurations, UVM Factory
  • UVC Development for Industry Standard Protocol
  • UVM Project
  • Explanation of IP, VIP, SOC Level Testbench flow, Testplans, Verification plan
Communication Protocols

  • SPI
  • UART
  • I2C
  • AMBA
  • PCIE
  • Ethernet
Future Trends in RTL Design & Verification

  • Integration of machine learning: Using machine learning algorithms to improve validation processes and refine design.
  • Automation: Ensure efficient and accurate automation of the design and analysis process.
  • Cloud-based tools: Use cloud-based tools for RTL design and validation to facilitate collaboration and increase productivity.


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Devikarani H S
7+ years of RTL DV experience

Devika brings 7+ years of RTL DV experience . She has experience in RTL Design and Verification. The trainer has worked on protocols like AXI , Ethernet and USB. Devika has a passion for teaching and training students/colleagues. She is an excellent team player and has mentored more than 50 students.



    Course Rating

    4.9 average rating based on 8 rating

    4.9
    (8 Review)
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    Course Includes:

    • Price:Rs.10000-70000
    • Instructor:Devikarani H S
    • Duration:300 Hours
    • Lessons:8
    • Enrolled: students
    • Language:English
    • Certificate:yes

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